1. Field of the Invention
This invention relates in general to a method and apparatus for retiming test signals, and more particularly to a test signal retiming circuit that is resistant to timing variations.
2. Description of Related Art
Designers need an easy way to test in order to establish rapid prototyping of designs in a test environment. Test methodologies help a design engineer structure the simulation of a circuit. These test methodologies can efficiently reuse simulation stimuli and response for a real device under test. Also, these modern test approaches increase the efficiency of the engineer in a test environment.
The technological evolution in microelectronics has lead to the ever-increasing complexity of systems integrated on high density chips. Since development and test time should not grow at the same rate as the complexity, new design and test methods are needed.
There's a whole new category of devices that are troubling test engineers in the digital industry. Test systems availability and hardware dependencies are a few limitations that plague a test engineer. To deal with the limitations, many hardware manufactures prefer digital testers as part of their automated test equipment. They also want a consistent testing environment that provides all the digital performance they need and reduces test development time by providing a consistent digital test methodology for all tests.
Manufacturer's need an integrated solution for the high-throughput production test coverage required to ensure quality in digital-dominant integrated circuits. Testing such devices requires the full functionality of a digital tester. Attributes such as high pin counts, high data rates and timing flexibility, combined with digital test methodologies now need to be coupled with the ability to test digital cells.
A digital testing devices has several advantages. It allows the designer to check for design-for-testability success at a much earlier stage during the manufacturing process. Also, errors are discovered before mass production is initiated. This greatly improves the likelihood of a correct designs earlier in an engineering effort.
One important aspect of digital test systems is the ability of the system provide a timing reference signal to detect correct digital output when sampling an output signal. The device must be insensitive to external stimuli and variations in hardware performance. During digital testing using automated test equipment, device inputs are driven by a set of digital vectors and device outputs are strobed by a tester and compared to reference data. Depending on the functionality, design implementation, process variation, tester, loadboard, interface hardware and output data detection, there are significant variations in clock skew and data arrival during clock periods.
For example, a tremendous problem in industrial digital testing is to identify variability of the data arrival and clock skew during the output data detection. Another problem is positioning the test timing strobe to detect a rise and fall of a signal edge consistently. Nevertheless, non-consistency directly effects repeatability of the test process, which in turn presents a problem for high volume production.
With increases in device operating frequencies and reduction in component size, this task becomes even more difficult. Deep submicron processes create further sources of timing variability. Test periods are reduced significantly without improvements in output data detection, and device timing accuracy approaches the automatic test equipment timing resolution.
It can be seen then that there is a need for test signal retiming circuit that consistently detects valid output data.
It can also be seen that there is a need for a test signal retiming circuit that is resistant to timing variations.
It can also be seen that there is a need for a test signal retiming circuit that ensures that the output data consistently is synchronized with the automatic test equipment.